Current Projects
ECE 337 Course Redesign
Over summer 2024, I worked with Eric Rodenkirch and Jacob Chappell on a revision of the ECE 337 ASIC Design Laboratory content and tools. This included rewriting each of the 11 lab manuals used throughout the semester, reorientation of lab content to resolve known issues, and overhaul of the grading, submission, and lab distribution systems into a stable, maintainable system.
I led my coworkers in the redesign all 5 introductory labs to better organize content and enhance clarity and fairness across all tasks required of students. We took the same approach to the four major design lab manuals, preserving the content but presenting it in an all-new way to keep as much student focus and time on design effort and learning over detangling requirements and deadlines.
In addition, I advised and reviewed work on the build system, primarily work done by Jacob. The new system is as amazing as it is easy to use, giving students a more transparent view of the EDA tools and how to manipulate designs for simulation, verification, and synthesis. This project has demonstrated great success among students in the Fall 2024 semester and has made both our Graduate and Undergraduate Teaching Assistants more effective in providing quality help to our students.
We continue to revise, update, and correct our manuals and lab assignments to better teach the foundations of ASIC design, using feedback from our Undergraduate Teaching Assistants and students. We plan to add homework assignments to better reinforce concepts taught in the course and better prepare students for what they should expect to see on an exam.
Wallace Tree Hardware Multiplier Schematic and Layout
I worked with Malcolm McClymont on the transistor-schematic and silicon layout for a hardware multiplier, implementing a Wallace Tree compressor and a Brent-Kung Adder for partial product summation. This involved the planning of Half and Full Adder components, the Brent-Kung Parallel Prefix Adder, and large-scale routing of hardware submodules. This project focused on module layout planning, learning Cadence Virtuoso, and designing for minimal area given power and speed constraints.
See the report for this project here.
Out-of-Order Processor Modifications in the Gem5 Simulator
I worked with Jacob Chappell and Timmy Hein on modifying the Gem5 source code in pursuit of a research-grade microprocessor improvement, specifically focused on cache optimization in an out-of-order context. We chose to implement the Shepherd Cache, an augmentation of the L2 cache, to improve cache replacement behavior by more closely mimicking the omniscient optimal replacement policy, OPT, in order to decrease the miss rate of a higher-order cache.
See the report for this project here.
Highlighted Projects
NES Hardware Emulator
I worked with Eric Rodenkirch, Anthony Butera, and Grant Daniel on a Hardware Emulation of the Nintendo Entertainment System, using an FPGA connected to original game cartridge and controller hardware. The project involved re-engineering of the CPU and internal coprocessors for the system, development of PCB hardware for interconnecting 1980s components with modern FPGAs, and building a chassis to stabilize critical electronics components alongside large human-interactable I/O pieces.
My main task was the reverse-engineering of the Picture Processing Unit, a proprietary video coprocessor designed specifically for the NES. Thus, it has no listed specification online. I took the work of many retro enthusiasts who had broken down its behavior and built back up the internals of the device, using those behavioral descriptions as ASIC requirements. The project involved implementing Memory-Mapped I/O, a Direct Memory Access Engine, a pixel rendering pipeline, color data lookup, and frame and scanline buffers.
Three specific challenges I encountered stood out:
- In interfacing with the CPU through memory-mapped I/O, I was met with multiple clock rates meeting at the memory. With the CPU slower, I had to ensure to not double-count or triple-count reads and writes from the CPU, some of which would increment counters or shift bits internal to the PPU.
- Certain flags and register transistions happened at different points in a frame. Timing these and debugging them was tricky, especially at the point when deploying changes to the Development Board and playing Super Mario was the best way to test if fixes worked. In particular, the flag used to detect the first sprite on the board had narrow timings and a number of conditions required for it to go high in addition to the first sprite's position. Malfunctions on the flag made games either not play or play in a very faulty manner.
- Lastly was the series of internal memory buffers used for storing the tiles, built as SRAM. Though contiguous in the PPU's memory system, they were built as separate SRAM blocks. Having them play nicely together and masking different portions off correctly, including performing virtual mirroring of memory sections, was difficult to complete. They interacted with internal D-FF buffers and LUTs, as well, in order to generate an image properly. Working these parts of the system was like conducting an orchestra.
In addition to my own work, I learned a lot from collaborating with my teammates and fulfilling course assignments regarding the technical, legal, regulatory, and commercial considerations with product design and pushing a product to market. A sincere thanks to my teammates on all their outstanding work and support, as well as helping our team win two awards for our project.
Chronomancer Out-of-Order Processor
Sparked by the ECE 565 Computer Architecture course and a further interest in understanding the inner workings of the R10K architecture, register renaming, the Reorder Buffer, Load-Store Queues, and applying my far greater SystemVerilog experience to processor design, I have assembled a team for constructing a modular RISC-V Out-Of-Order Microprocessor.
In the works with Eric Rodenkirch, Jacob Chappell, Spencer Bowles, Atthin Chandrashekar, Matt Erlichson, Malcolm McClymont, and myself, we are building an FPGA-deployable SystemVerilog implementation of an out-of-order microprocessor complete with internal profilers and parameterized components for verification and optimization.
We are also taking the opportunity to learn UVM, something we've noticed to be a hole in our curriculum that prospective employers want from us.
Past Projects
In-Order Dual-Core Coherent MIPS Processor
Along with Timmy Hein, we worked on the semester-long processor design laboratory component of ECE 437. This included completion of a single-cycle core, five-stage pipelined core, L1-style instruction and data caches, a memory bus controller, cache coherence, and multicore support. This culminated in a dual-core, coherent pipelined processor.
What I took away most from this work was the little things in computer architecture: Stalls, Forwarding and Bypassing, Branch Prediction, Instruction Fetch, and Latched Memory Bus behavior. It provided me with a respect for the implementation details associated with small optimizations, as well as the enormous lengths the field will go to for just a bit more performance.
The course also provided me with nontechincal intangibles. I gained a much greater appreciation for Computer Architecture, and a desire to find a job in the field. I learned more about how to manage a version-controlled project effectively (sometimes through painful lessons) and translated that wisdom to both my senior design project and my work on the course overhaul as a Graduate TA. Lastly, I was rewarded with leisure and a sigh of relief when we worked hard and worked together to finish the final integration of the Dual-Core component three weeks before the deadline. The resultant lack of stress nearing finals week told me, in action, all the benefits of being ahead in a big project like this.
Quantum Dot Design
For the first of two projects in my Solid State Devices course, I worked with teammates to build an optical quantum dot for specific absorption and emission characteristics. This devices is what is used in QDOT LED TVs and other optical devices. We used simulation tools from NanoHub to design, modify, and optimize our device, as well as exploring a variety of industry-grade techniques, highlighted by our use of strained silicon for optimal performance.
See the report for this project here.
Nanowire Transistor Design
For the second of two projects in my Solid State Devices course, I worked with teammates to build a Nanowire Gate-All-Around transistor and analyze the effects of device scaling on it and other transistor varieties, such as bulk and FinFET. We evaluated important metrics like On/Off ratios and Subthreshold Swing for our devices at different sizes.
See the report for this project here.
LLM Watermarking Engine
I tackled the review and enhancement of software module built to leave a traceable footprint in the text output of a large language model. It does this by modulating the probabilistic behavior of the LLM's output layer, creating a set of more likely words that swing the text out of normal distribution. It then runs the algorithm again on the text, comparing the shifted distribution to the text under scrutiny. I modified the detection code to work for subsets of a large text corpus, catching AI-generated text paragraphs from OPT-6 and GPT-2 that are inserted into a larger human work.
See the reports for this project here and here.
Surface Codes
I worked with Spencer Bowles, Aidan Jacobsen, and Zach Fielding to research an algorithm used in Quantum Computing. We chose to unravel the technique of Surface Codes, used for dense Quantum Error Correction. This included understanding the mathematical background, formulation, and application of these codes for QEC, as well as their effectiveness for keeping Quantum Computers stable.
Eagle Scout Service Project
On the road to reaching the rank of Eagle Scout, Scouts are asked to plan and complete a service project that benefits their community. Following a $2.5-Million rennovation to the church that my family were members of and that hosted our troop, the community's Youth Group was left without a permanent room to hold meetings and events in. I saw this as an opportunity and chose the fundraising for, design of, and bringing-to-life of a dedicated space as my Eagle Scout Service Project.
For fundraising, I solicited direct donations from Friends, Family, and the congregation at large. I also planned and hosted a during-the-service, pay-what-you want carwash for congregation members as a fundraising event. Both were incredibly successful and led to having over $3000 for the planning and implementation of the new space.
In addition to planning seating, rugs, bookshelves, wall decor, and even a mini-fridge, I also worked with the Youth Group's new youth leader to understand the unique needs of their space. As this project took place shortly after the group's service trip to South Carolina (from our home in Massachusetts), he wanted to bring a special piece of that trip back to the room. Our choice was a game they had played that involved a long carpeted table and pool balls, popular at summer camps and in similar environments. I designed a table for the game with the help of a local craftsman and then sourced materials.
In the execution phase of the project, I learned more about money management, keeping traceable records, inventory management, and budgeting. I held a pair of build-days, common with scout service projects, where other members of my troop assisted with table construction. I was able to add the finishing touches after the second section and tested its functionality to have some fun.
The room came together and I had a decorating day with some of the Youth Group members, certifying the space as their home. In the end, we had almost $150 remaining which was donated to the group to support future activities and supplies.
I'm proud of the work I did as a 10th-grade high school student, nearly 7 years on, and I'm happy to have given back to people I'd known for over a decade. I found that the greatest value in that building was community, both scouting and religious, and I was awestruck at the level of support others are wiling to give for a cause.
USB Transceiver ASIC
Along with Eric Rodenkirch and Anthony Butera, we tackled ECE 337's final project, the USB 1.1 Transceiver. This consisted of four elements: a USB Receiver, USB Transmitter, AHB-Lite Bus Interface, and a central Data Buffer for passing packet contents.
I tackled the Bus Interface and Data Buffer. This led to an exploration of hardware data structures, memory-mapped I/O, and forced me to understand the process of testbenching much better. It also gave me a healthy respect for the integration phase of a project, stemming from mistakenly putting it off as a team. This translated with these same team members to much better project planning for our Senior Design work.
I have now gone on to teach this project to new generations of students no fewer than five times. I think it's a great, challenging project that allows students to demonstrate their understanding while still fitting the bill for an introductory design course like ECE 337.
Courses
Hardware Design Coursework:
ECE 337: ASIC Design. I learned principles of application-specific IC design using a SystemVerilog, QuestaSim, and Design Compiler toolchain. I've gone on to be an undergraduate and graduate teaching assistant for this course, including rewriting each of its lab manuals, assisting with a build system overhaul with Jacob Chappell, and injecting AI Hardware content into the course.
ECE 437: Computer Design and Prototyping. I learned the principles of pipelined processor design, cache design, virtual memory, and multicore systems in this course, along with acquiring tools for analyzing computer performance and evaluating design improvement choices. The lab portion of the course was the hardest and most rewarding portion of the course, and culminated in a functional MIPS Dual-Core processor that I worked on with my partner Timmy Hein.
ECE 477: Digital Systems Senior Design Project. I worked with Eric Rodenkirch, Anthony Butera, and Grant Daniel on a Hardware Emulation of the Nintendo Entertainment System using an FPGA connected to original game cartridge and controller hardware. In addition to my role working on the graphics processor using my SystemVerilog and Testbenching skills, I bolstered my project management, project organization, and project leadership experience over the course of this capstone project.
ECE 565: Computer Architecture. In this class, I've learned about Out-of-Order Processing and Register Renaming concepts, as well as architectural advances like branch predictors, LS Queues, Superscalar architectures, and SRAM design considerations. I've also learned how to use and modify the Gem5 simulator for this course. I'm looking forward to learning more about cache hierarchies, memory systems, and vector processing. I'm working with Jacob Chappell and Timmy Hein on a cumulative project in Gem5 for this course. It has also inspire the creating of my planned Chronomancer Processor Design project.
ECE 559: MOS VLSI. I've learned Cadence's Virtuoso Layout tools for this course, in addition to reviewing transistor physics and CMOS design. Most importantly for hardware design is the derivation of gate delays and digital circuit timing from physically-based RC response times for interconnects and silicon devices. I'm working with Malcolm McClymont on a Hardware Multiplier and Multiply-Accumulate unit laid out in silicon. I'm looking forward to expanding my understanding of more complex gates, layout heuristics, and best practices for Circuit Design.
ECE 60827: Programmable Accelerator Architectures (Upcoming). This the premier GPU/Accelerator/SIMD course from Purdue and I hope to learn about highly parallel computation, the inner workings of graphics cards, render pipelines, and CUDA programming. I'm also excited for the parallels between this course and the AI Hardware Accelerator content I'm working on developing with SCALE. This course will be taught by Prof. Vijaykumar, so I know it will be a blast.
Semiconductor Coursework:
ECE 305: Semiconductor Devices. This course taught me numerical approaches to transistor physics, energy band diagrams, PN Junctions, MOSCaps, MOSFETs, and BJT basics. It taught me how to visualize both the physical and energy spaces of devices and showed me how standard RLC components function on the small scale.
ECE 50653: Fundamentals of Nanoelectronics. This course consisted of three modules on current flow, quantum transport, and Boltzmann's Law. The first module taught me new ways to think about current, conduction, and introduced to me the idea of ballistic transport, as well as supplementing my understanding of E-k dispersion and Density of States. The second module reinvented how I think about the Schrödinger equation, energy barriers, and tunneling. The third module blew me away with equilibrium statistical mechanics, taught me Markov Chain Monte Carlo approaches to systems behavior, and made me endlessly curious about quantum computing and machine learning. Supriyo Datta is an amazing lecturer and instructor.
ECE 606: Solid State Devices I. This course taught me quantum physics approaches to band diagrams from E-k dispersions, numerical approximation, drift-diffusion, and a variety of semiconductor materials. In addition, it taught ECE 305 concepts like PN-diodes, MOSFETs, and BJTs in more detail while also exposing me to nonidealities, nanoscale devices, and HBJTs. I learned to use the tools on NanoHub for simulation and design evaluation, culminating in my project work on Quantum Dots and Nanowire Gate-All-Around Transistors.
ECE 559: MOS VLSI. This course also had semiconductor physics, especially regarding the calculations of delays and capacitance in CMOS gates from the perspective of transistor physics. My transistor experience from ECE 606 played a part in my success here.
ECE 60645: High-speed Semiconductor Devices (Upcoming). This course interests me as it covers modern topics like High-K Dielectrics; the MESFET, JFET, and HFET; strained silicon; and work into Terahertz transistor switching. I hope to build a strong base of understanding in these topics that gives me a competitive edge in designing physical circuits and architecting digital systems.
AI Coursework:
ECE 570: Introduction to Artificial Intelligence. Learned the basics of AI Theory and AI Algorithms implementation in Python. Covered dimensionality reduction, classification, function approximation with neural networks, and basic generative algorithms. Pursued a project in LLM Watermarking, a technique for encoding traceable patterns into text output from Language Models, and upgraded the engine for subsection detection in large text corpi.
ECE 595-RL: Reinforcement Learning Theory and Algorithms. Covered the deep mathematics of reinforcement learning, performing policy and value optimization, and exploring Q-learning. This was some of the most challenging course content I've seen at Purdue, but was very eye-opening nonetheless.
ECE 695-GM: Inference and Learning in Generative Models. Started at a Graphical Model framework for performing inference and generation, as well as classifying different approaches to machine learning. Contextualized and connected loss components, like entropy, cross-entropy, and KL Divergence to better explain the process of learning and the learning manifold, as well as explaining the EM algorithm, variational strategies, and other learning paradigms. Very cutting-edge math and research involved in the course!
Math Coursework:
Calculus, Linear Algebra, Differential Equations, Graduate Graph Theory, Graduate Numerical Methods (Upcoming)
Other Interesting Coursework:
- NUCL 200: Introduction to Nuclear Engineering. The hardest undergraduate course I took at Purdue, even more so than ECE 437. Covered nuclear physics, heat transfer, reactor design theory, and generations of reactor designs. Not in my wheelhouse but wildly interesting and satisfying to overcome such a challenge.
- ECE 595-AQC: Applied Quantum Computing. Learned QBit Theory, Quantum Circuits, Quantum Algorithms, and Quantum Error Correction. Undertook a cumulative project and presentation on Surface Codes with Spencer Bowles, Aidan Jacobsen, and Zach Fielding
- ECE 382: Feedback System Analysis and Design. Controls was a favorite class out of the 300-levels for me, and I found the use of feedback in systems clarified my understanding of not only how robotics works, but also how computers operate with respect to storing state and computing with feedback loops in Moore Machines.
- ECE 39595O: Object-Oriented Programming with C++. Learned more about C++ and worked on projects like a chess engine and hash maps. Learned I do not like the OOP paradigm over function-based programming.
- ECE 270: Introduction to Digital Design. I took this class with a great professor, Rick. I learned a ton about digital logic, digital circuits, breadboarding digital circuits, and how to write SystemVerilog. Loved this class and served as a TA for a semester.
- ECE 362: Microprocessor Systems and Interfacing. Learned about microprocessors, writing code for Micros in C, I/O interfacing, and the basic processor datapath.
Other Relevant Coursework:
- ECE 20001: Electrical Engineering Fundamentals I.
- ECE 20002: Electrical Engineering Fundamentals II.
- ECE 20007: Electrical Engineering Fundamentals I Lab.
- ECE 20008: Electrical Engineering Fundamentals II Lab.
- ECE 301: Signals and Systems.
- ECE 302: Probabilistic Methods.
- ECE 30411: Electromagnetics I.
- ECE 264: Advanced C Programming.
- ECE 368: Data Structures and Algorithms.
- ECE 20875: Python for Data Science.
These courses generally serve as foundations and prerequisites for others. I found 301 and 302 particularly interesting, and 30411 was the best of the bunch. I also learned that physical circuit design and breadboarding is harder for me to get an intuitive grasp on than coding is. I learned I'm better at Python than C, and that I underestimate how long getting a C Programming Assignment working takes me. I found that I like the challenge of design better than the challenge of learning a programming language, and found I enjoy few harder problems rather than many easier problems on homework.